1. Field of the Invention
The invention relates in general to a charging/discharging circuit and a phase-locked loop (PLL) circuit using the same, and more particularly to a charging/discharging circuit without a capacitor and a PLL circuit using the same.
2. Description of the Related Art
FIG. 1 shows a block diagram of a phase-locked loop (PLL) circuit 100 in the prior art. As shown in FIG. 1, the PLL circuit 100 includes a phase detector 101, a charge pump 103, a loop filter 105 and a voltage-controlled oscillator (VCO) 107. The phase detector 101 compares phases of a reference signal Sref and an output signal Sout, so as to control the charge pump 103 to charge/discharge the loop filter 105 and to control an output voltage VC of the loop filter 105. More specifically, the loop filter 105 further includes energy storage elements such as capacitors or inductors. The control voltage VC is increased when a current for charging the loop filter 105 is provided to the loop filter 105, and alternately the control voltage VC is reduced when a current for discharging the loop filter 105 is drawn from the loop filter 105.
The VCO 107 receives the control voltage VC and generates the output signal Sout. In general, the VCO 107 increases the frequency of the output signal Sout as the control voltage VC rises, and reduces the frequency of the output signal Sout as the control voltage VC lowers. The above design may vary for different circuit designs. Therefore, when the phases of the reference signal Sref and the output signal Sout are different, the control voltage VC can be modified to change the frequency of the output signal Sout (thereby also changing the phase of the output signal Sout). With the above mechanism, the phase of the output signal Sout can be synchronized to that of the reference signal Sref. On a path from the VCO 107 to the phase detector 101, the PLL circuit 100 may include a frequency divider for adjusting the output signal Sout. For example, assume that the reference signal Sref is a 100 MHz clock signal, and the frequency range provided by the VCO 107 however does not cover 100 MHz. At this point, the VCO 107 may first generate the output signal Sout in a higher frequency of 400 MHz, and the 400 MHz output signal Sout is then divided by 4 using the frequency divider. The phase detector 101 next compares the reference signal Sref with the frequency-divided output signal Sout. As such, the VCO 107 is not required to have an extremely broad frequency range, while the phase detector 101 may also yield a more precise comparison result from comparing two clock signals in lower frequencies.
The charge pump 103 may be implemented in different structures. In one of the structures, a current is provided to the loop filter 105 or drawn from the loop filter 105 according to an up signal or a down signal. As previously described, the control voltage VC is increased when a current is provided to charge the loop filter 105, and alternately the control voltage VC is decreased when a current for discharging loop filter 105 is drawn from the loop filter 105. Hence, the control voltage VC output by the loop filter 105 can be controlled through the above method. More specifically, the phase detector 101 compares the phases of the reference signals Sref and the output signal Sout to accordingly generate an up signal UP or a down signal DN. When the up signal UP is received, the charge pump 103 generates an up current IUP for charging the loop filter 105 to further increase the control voltage VC. Conversely, when the down signal DN is received, the charge pump 103 draws a down current IDN from the loop filter 105 to discharge the loop filter 105 and to further decrease the control voltage VC. Thus, the VCO 107 changes the frequency of the output signal Sout according to the control voltage VC.
FIG. 2 shows a circuit diagram of a charge pump 200 controlled by an up signal and a down signal in the prior art. As shown in FIG. 2, the charge pump 200 includes a reference current providing module 201, capacitors 203 and 207, switch modules 205 and 209, and bias transistors BT1 and BT2. The capacitor 203, the switch module 205 and the bias transistor BT1 may be collectively regarded as an up current module 204. When an up signal UP turns on the switch module 205, the up current module 204 provides an up current IUP to the loop filter 202. The capacitor 207, the switch module 209 and the bias transistor BT2 may be collectively regarded as a down current module 206. When a down signal DN turns on the switch module 209, the down current module 206 draws a down current IDN from the loop filter 202.
The purpose of the capacitor 203 is to stabilize the supply of the up current IUP and the purpose of capacitor 207 is to stabilize the ability to accept the discharged down current IDN. For example, when the down signal DN is at a high level, the switch module 209 is turned on to start drawing the down current IDN. However, at the same time, the voltage level to the control terminal of the bias transistor BT2 is also reduced, such that the bias transistor BT2 may no longer allow down current IDN to flow from the loop filter 202 to the switch module. Thus, in the absence of the capacitor 207, after turning on the switch module 209, the bias transistor BT2 may be soon turned off such that the discharging process of the down current IDN is inefficiently performed. Thus, without the capacitor 207, the down current IDN cannot be rapidly drawn from the loop filter 202, leading to a reduced speed in adjusting the control voltage VC by the loop filter 202. Likewise, the analogous problem would occur to the up current module 204 in the absence of its capacitor 203. Namely, without capacitor 203, up current module 204 cannot rapidly charge loop filter 202 with up current IUP in response to up signal UP. Consequently, the PLL circuit utilizing the charge pump may fail to provide signals of a required phase in a fast and efficient manner without the use of capacitors. The problem is that capacitors occupy a substantial area. More particularly, the area occupied by one capacitor frequently makes up about one-half of the area occupied by the entire charge pump. Thus, in the prior art, the conventional mechanism utilizing fixed capacitors for stabilizing the provision of the up current IUP and the drawing of the down current IDN yields a large-area microelectronic component, which does not satisfy the increasing miniaturization requirements of modern electronic devices.
Therefore, there is a need for a new circuit for solving the above issues.